Job Description

Must be a US Citizen or Green Card Holder

The Work:

• Port ASIC and IP RTL code to prototyping and emulation platforms (Zebu/HAPSs, Palladium/Protium)
• Build model from released RTL
• Generate loadable image(s) for target prototyping and emulation platform
• Run sanity tests to qualify release of the image(s)
• Release the emulation/prototyping images to various teams doing functional validation, firmware development and design verification
• Assist debug of failures with stakeholder by providing instrumented models and captured waveforms extracted from in-circuit debug logic
• Coordinate with EDA and prototyping tools team to validate implementation flows

Here’s what you need:

• A minimum 4 years of experience in Emulation, Prototyping or FPGA design and verification using System Verilog/Verilog/VHDL
• A minimum of 4 years of experience with porting ASIC/IP RTL to Emulation platforms: Zebu/HAPSs, Palladium/Protium
• Unix/Linux development environments and scripting languages like Tcl, Python, C-shell
• Logic simulation: VCS/Xcelium
• Strong knowledge of Complete Design Cycle to understand the Different IP designs to integrate in the build
• Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)

Bonus points if:

• Good knowledge of SoC design methodologies and technologies, with experience in the complete design validation cycle
• Knowledge of key protocol’s like PCIe, USB, Ethernet, AMBA, UART, DDR, flash memories and their usage in SoC environments
• Experience with CPU integration is a big plus, especially ARM/RISC-V CPU
• Knowledge of CoreSight/UltraSoC debug infrastructure integration
• Familiarity with IO's such as MIPI CSI & DSI, USB, PCIE, LPDDR
• Experience with lab system debug with logic analyzers, scopes, meters etc.
• SoC experience with bare-metal code
• Post silicon bringup

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